These are my notes regarding the Open-Source IC design tools including their setup and usage. I will also try and post any tips and tricks that I find helpful.

Digital Design

Setup

[!NOTE] I have more or less just been using the oss-cad-suite tools for my developoment with Tiny Tapeout, then push to Github for doing the gate-level synthesis.

I like to keep my EDA tools (particularly ones that modify the environment) out of my main system path. The OSS-CAD-Suite conveniently has a activation script to facilitate this use case, this is in line with the commercial EDA tools. It is particularly useful so that multiple versions of the tools can be installed at the same time without conflict. Install the CAD suite by extracting the release to a directory of your choice (I install to ~/.local/extra_packages/oss-cad-suite). To use the tools, you need to activate the environment, do this by running source <path to suite>/activate. However, I don’t like having to remember exactly where I put my tools in the path, so I use a “startup script” that I can copy to my project directory to activate the correct environment for me.

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# Startup.OSS-CAD-Suite
# Activate environment by running "source Startup.OSS-CAD-Suite"
OSS_CAD_HOME="$HOME/.local/extra_packages/oss-cad-suite"
source "$OSS_CAD_HOME/environment"

Now, when I am in my project directory, I can just call

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source Startup.OSS-CAD-Suite

and the cad suite environment will be set up for me. This is also very helpful for managing multiple versions of tools as I can have multiple startup scripts that source the activation script that was installed to an alternate directory.

Tiny Tapeout Local Installation

Tiny Tapeout uses openlane (typically applied using github actions), and it is possible to run the commands locally on a personal computer.

On linux we can simply proceed with the installation instructions, but on Windows WSL2 must be set up first in order to have a Linux environment we can work with for Podman/Docker (WSL2 setup instructions)[https://learn.microsoft.com/en-us/windows/wsl/install].

Environment Setup (Everything Local)

We need Python 3.11 and a number of tools for the Tiny Tapeout flow to work to begin, we will install the appropriate python version and setup a virtual environment.

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sudo apt update
sudo apt install -y python3.11 python3.11-venv python3-pip git build-essential

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python3.11 -m venv tt_venv
source tt_venv/bin/activate
pip install -r tt/requirements.txt
pip install -r tt/precheck/requirements.txt

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source tt_env
pushd .
cd $OPENLANE_ROOT
make
pushd

make a directory to build the output in

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mkdir runs
chmod a+rw runs

run the synthesis flow

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docker run --rm -v $OPENLANE_ROOT:/openlane -v $PDK_ROOT:$PDK_ROOT -v $(pwd):/work -e PDK=$PDK -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) $OPENLANE_IMAGE_NAME /bin/bash -c "./flow.tcl -overwrite -design /work/src -run_path /work/runs -tag wokwi"

First, we will install (pyenv)[https://github.com/pyenv/pyenv?tab=readme-ov-file#installation].

In the shell run

curl https://pyenv.run | bash

then we will need to setup the environment for pyenv

Environment Setup (Docker/Podman)

To start we need to setup the docker containers for OpenLane

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podman pull registry.hub.docker.com/efabless/openlane:eaba5192c45aa333ab45216ce1773d75d539e9b3-amd64
git clone --depth=1 --branch $OPENLANE_TAG https://github.com/The-OpenROAD-Project/OpenLane.git $OPENLANE_ROOT

To start we need to setup some environment variables Linux/Mac:

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mkdir my-local-design-files
export DESIGNS=$HOME/my-local-design-files

Next we will use Podman/Docker to install the efabless ASIC tools

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podman pull registry.hub.docker.com/efabless/foss-asic-tools

This will take a while and use about 8GB(?) of disk space

We can run the image using the command

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podman run -it -p 80:80 --user $(id -u):$(id -g) -v \
  "$DESIGNS:/foss/designs efabless/foss-asic-tools:latest bash"

The directory my-local-design-files will reside on the hard disk of the host computer but will be mounted by the docker image at start-up. It will essentially act as a link between the host computer and the design environment

Random Tips

Generating Block Diagrams

I don’t like the dot output that yosis generates by default, and much prefer the output from netlistsvg. Using the following shell script, json output from yosis can be copy-pasted into the tool to generate block diagrams.

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#! /bin/bash
# Run Yosys to generate an elaborated netlist of a Verilog Module
# JSON output is copied to clipboard for pasting into netlistsvg
# Author: Sam Ellicott
# Date: October 30, 2024
# Useage: elaborate_json.bat <top level module> <input file>

# Check parameters and generate useage message
echo "Useage: <top level module> <input file>" 

# Run yosys and generate the json output file
yosys -p "prep -top $1; write_json output.json" ${@:2}

# copy JSON output to clipboard
xclip < output.json
echo "JSON copied to clipboard"

Analog Design

Basic Analog Design Course

analog design course

Get the tools for analog design here

Links

• OSS-CAD-Suite: Digital Synthesis tools and formal verification
  • Amaranth: Python HDL and testbench tool bundled with the OSS-CAD-Suite.
  • Make the Synthesized output pretty with netlistsvg
• sky130 Standard Cells For some reason this isn’t in the official documentation
• Verible configuration for Verilog Helpful tip for getting verible to work with Verilog projects